The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang; Ming-Dou Ker; Tai Xiang Lai; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang^*, Ming-Dou Ker, Tai Xiang Lai, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

Original language	English
Title of host publication	Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
Pages	249-252
Number of pages	4
DOIs	https://doi.org/10.1109/IPFA.2007.4378094
State	Published - 1 Dec 2007
Event	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India Duration: 11 Jul 2007 → 13 Jul 2007

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Country/Territory	India
City	Bangalore
Period	11/07/07 → 13/07/07

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10.1109/IPFA.2007.4378094

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Chang, W. J., Ker, M.-D., Lai, T. X., Tang, T. H., & Su, K. C. (2007). The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. In Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007 (pp. 249-252). Article 4378094 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2007.4378094

Chang, Wei Jen ; Ker, Ming-Dou ; Lai, Tai Xiang et al. / The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. pp. 249-252 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{b87ab658198f4908b1929de6fd5e9bac,

title = "The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process",

abstract = "The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.",

author = "Chang, {Wei Jen} and Ming-Dou Ker and Lai, {Tai Xiang} and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IPFA.2007.4378094",

language = "English",

isbn = "1424410142",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "249--252",

booktitle = "Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007",

note = "2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits ; Conference date: 11-07-2007 Through 13-07-2007",

}

Chang, WJ, Ker, M-D, Lai, TX, Tang, TH & Su, KC 2007, The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. in Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007., 4378094, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 249-252, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Bangalore, India, 11/07/07. https://doi.org/10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. / Chang, Wei Jen; Ker, Ming-Dou; Lai, Tai Xiang et al.
Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 249-252 4378094 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Su, Kuan Cheng

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N2 - The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

AB - The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

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Chang WJ, Ker MD, Lai TX, Tang TH, Su KC. The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process. In Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 249-252. 4378094. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2007.4378094

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

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