The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

Yu Shu Shen, Ming Dou Ker

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications.

Original languageEnglish
Pages (from-to)2152-2159
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume68
Issue number5
DOIs
StatePublished - 20 Jul 2021

Keywords

  • Electrical fast transient (EFT)/burst test
  • Electrostatic discharges
  • holding voltage
  • Integrated circuits
  • Microelectronics
  • Pins
  • signal integrity
  • system-level electrostatic discharge (ESD)
  • Transient analysis
  • transient voltage suppressor (TVS).
  • TV
  • Voltage measurement

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