The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology

The dependences of drift implant and layout parameters on electrostatic discharge (ESD) robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better transmission line pulsing (TLP)-measured secondary breakdown current (It2) and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon-controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and human-body-model ESD levels on the spacing from the drain diffusion to polygate are different.