TY - GEN
T1 - The first Ge nanosheets GAAFET CMOS inverters fabricated by 2D Ge/Si multilayer epitaxy, Ge/Si selective etching
AU - Chu, Chun Lin
AU - Luo, Guang Li
AU - Chen, Shih Hong
AU - Chang, Wei Yuan
AU - Wu, Wen Fa
AU - Yeh, Wen Kuan
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/4/19
Y1 - 2021/4/19
N2 - Stacked Ge nanosheets (NSs) GAA FET CMOS inverters are demonstrated for the first time. In this work, for formation of well-defined stacked Ge NSs, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material for the following better selective etching between Ge/Si. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to be removed than the case that Ge layers are still tied with Si layers. Finally, a functional Ge NSs GAAFET CMOS inverter with maximum voltage gain of 25V/V was demonstrated.
AB - Stacked Ge nanosheets (NSs) GAA FET CMOS inverters are demonstrated for the first time. In this work, for formation of well-defined stacked Ge NSs, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material for the following better selective etching between Ge/Si. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to be removed than the case that Ge layers are still tied with Si layers. Finally, a functional Ge NSs GAAFET CMOS inverter with maximum voltage gain of 25V/V was demonstrated.
UR - http://www.scopus.com/inward/record.url?scp=85108172611&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA51926.2021.9440077
DO - 10.1109/VLSI-TSA51926.2021.9440077
M3 - Conference contribution
AN - SCOPUS:85108172611
T3 - VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
BT - VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021
Y2 - 19 April 2021 through 22 April 2021
ER -