The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test

Jian Hsing Lee*, Chih Hsuan Lin, Karuna Nidhi, Chao Yang Chen, Yeh Ning Jou, Ming Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The failure mechanism of latch-up in two different power domains for the high voltage (HV) output driver under the positive trigger current latch-up test is investigated. From the T-CAD, why the guard-rings (GRs) in two different power domains are damaged is found. It is caused by the conductivity modulation effect as the region between two power domains is triggered into the latch-up state. So, this region becomes an intrinsic region (resistor) to induce power short to power, resulting in the GR damage.

Original languageEnglish
Title of host publication2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665498159
DOIs
StatePublished - 2022
Event2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022 - Singapore, Singapore
Duration: 18 Jul 202221 Jul 2022

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2022-July

Conference

Conference2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2022
Country/TerritorySingapore
CitySingapore
Period18/07/2221/07/22

Keywords

  • Bipolar CMOS DMOS (BCD)
  • Guard-Ring
  • Latch-Up Test
  • Positive Trigger-Current

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