The effect of IrO2-IrO2- Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-D GOI CMOSFETs

D. S. Yu*, C. C. Liao, C. F. Cheng, Albert Chin, M. F. Li, S. P. McAlister

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-Κ/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μm CMOSFETs. The devices used IrO2-IrO2-Hf dual gates and a high-Κ LaAiO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 mn. The metal-gate/high-Κ/GOI p-and n-MOSFETs displayed threshold voltage (Vt) shifts of 30 and 21 mV after 10 MV/cm, 85 °C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-Κ-Si CMOSFETs. An extrapolated maximum voltage of - 1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.

Original languageEnglish
Pages (from-to)407-409
Number of pages3
JournalIEEE Electron Device Letters
Issue number6
StatePublished - 1 Jun 2005


  • Bias-temperature instability (BTI)
  • Germanium-on-insulator (GOI)
  • High Κ
  • LaAlO
  • Metal gate
  • Three-dimensional (3-D)


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