The effect of IEC-like fast transients on RC-triggered ESD power clamps

Cheng Cheng Yen; Ming-Dou Ker

doi:10.1109/TED.2009.2017625

The effect of IEC-like fast transients on RC-triggered ESD power clamps

Cheng Cheng Yen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-μm CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a "latch-on" state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.

Original language	English
Pages (from-to)	1204-1210
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	56
Issue number	6
DOIs	https://doi.org/10.1109/TED.2009.2017625
State	Published - 28 Apr 2009

Keywords

ESD protection circuit
Electrical fast-transient (EFT) test
Electromagnetic compatibility
Electrostatic discharge (ESD)
Latchup
System-level ESD stress

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10.1109/TED.2009.2017625

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@article{337c702aaf2a4becb986f6a5ca91394e,

title = "The effect of IEC-like fast transients on RC-triggered ESD power clamps",

abstract = "Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-μm CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a {"}latch-on{"} state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.",

keywords = "ESD protection circuit, Electrical fast-transient (EFT) test, Electromagnetic compatibility, Electrostatic discharge (ESD), Latchup, System-level ESD stress",

author = "Yen, {Cheng Cheng} and Ming-Dou Ker",

year = "2009",

month = apr,

day = "28",

doi = "10.1109/TED.2009.2017625",

language = "English",

volume = "56",

pages = "1204--1210",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "6",

}

TY - JOUR

T1 - The effect of IEC-like fast transients on RC-triggered ESD power clamps

AU - Yen, Cheng Cheng

AU - Ker, Ming-Dou

PY - 2009/4/28

Y1 - 2009/4/28

N2 - Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-μm CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a "latch-on" state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.

AB - Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-μm CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a "latch-on" state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.

KW - ESD protection circuit

KW - Electrical fast-transient (EFT) test

KW - Electromagnetic compatibility

KW - Electrostatic discharge (ESD)

KW - Latchup

KW - System-level ESD stress

UR - http://www.scopus.com/inward/record.url?scp=67349240805&partnerID=8YFLogxK

U2 - 10.1109/TED.2009.2017625

DO - 10.1109/TED.2009.2017625

M3 - Article

AN - SCOPUS:67349240805

SN - 0018-9383

VL - 56

SP - 1204

EP - 1210

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

IS - 6

ER -

The effect of IEC-like fast transients on RC-triggered ESD power clamps

Abstract

Keywords

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