TY - GEN
T1 - Testing strategies for a 9T sub-threshold SRAM
AU - Yang, Hao Yu
AU - Lin, Chen Wei
AU - Chen, Hung Hsin
AU - Chao, Chia-Tso
AU - Tu, Ming Hsien
AU - Jou, Shyh-Jye
AU - Chuang, Ching Te
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.
AB - Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.
UR - http://www.scopus.com/inward/record.url?scp=84873125670&partnerID=8YFLogxK
U2 - 10.1109/TEST.2012.6401577
DO - 10.1109/TEST.2012.6401577
M3 - Conference contribution
AN - SCOPUS:84873125670
SN - 9781467315951
T3 - Proceedings - International Test Conference
BT - ITC 2012 - International Test Conference 2012, Proceedings
T2 - 2012 International Test Conference, ITC 2012
Y2 - 6 November 2012 through 8 November 2012
ER -