Testing retention flip-flops in power-gated designs

Hao Wen Hsu; Shih Hua Kuo; Wen Hsiang Chang; Shi Hao Chen; Ming Tung Chang; Chia-Tso Chao

doi:10.1109/VTS.2013.6548880

Testing retention flip-flops in power-gated designs

Hao Wen Hsu, Shih Hua Kuo, Wen Hsiang Chang, Shi Hao Chen, Ming Tung Chang, Chia-Tso Chao

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V _DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V_DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

Original language	English
Title of host publication	Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs	https://doi.org/10.1109/VTS.2013.6548880
State	Published - 14 Aug 2013
Event	2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States Duration: 29 Apr 2013 → 1 May 2013

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium

Conference

Conference	2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/Territory	United States
City	Berkeley, CA
Period	29/04/13 → 1/05/13

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10.1109/VTS.2013.6548880

Cite this

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title = "Testing retention flip-flops in power-gated designs",

abstract = "This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.",

author = "Hsu, {Hao Wen} and Kuo, {Shih Hua} and Chang, {Wen Hsiang} and Chen, {Shi Hao} and Chang, {Ming Tung} and Chia-Tso Chao",

year = "2013",

month = aug,

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doi = "10.1109/VTS.2013.6548880",

language = "English",

isbn = "9781467355438",

series = "Proceedings of the IEEE VLSI Test Symposium",

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note = "2013 IEEE 31st VLSI Test Symposium, VTS 2013 ; Conference date: 29-04-2013 Through 01-05-2013",

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T1 - Testing retention flip-flops in power-gated designs

AU - Hsu, Hao Wen

AU - Kuo, Shih Hua

AU - Chang, Wen Hsiang

AU - Chen, Shi Hao

AU - Chang, Ming Tung

AU - Chao, Chia-Tso

PY - 2013/8/14

Y1 - 2013/8/14

N2 - This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

AB - This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

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DO - 10.1109/VTS.2013.6548880

M3 - Conference contribution

AN - SCOPUS:84881273566

SN - 9781467355438

T3 - Proceedings of the IEEE VLSI Test Symposium

BT - Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013

T2 - 2013 IEEE 31st VLSI Test Symposium, VTS 2013

Y2 - 29 April 2013 through 1 May 2013

ER -

Testing retention flip-flops in power-gated designs

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