TY - GEN
T1 - Testing methods for quaternary content addressable memory using charge-sharing sensing scheme
AU - Yang, Hao Yu
AU - Huang, Rei Fu
AU - Su, Chin Lung
AU - Lin, Kuan Hong
AU - Shu, Hang Kaung
AU - Peng, Chi Wei
AU - Chao, Chia-Tso
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/30
Y1 - 2015/11/30
N2 - Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.
AB - Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.
UR - http://www.scopus.com/inward/record.url?scp=84958657239&partnerID=8YFLogxK
U2 - 10.1109/TEST.2015.7342409
DO - 10.1109/TEST.2015.7342409
M3 - Conference contribution
AN - SCOPUS:84958657239
T3 - Proceedings - International Test Conference
BT - International Test Conference 2015, ITC 2015 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 46th IEEE International Test Conference, ITC 2015
Y2 - 6 October 2015 through 8 October 2015
ER -