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Testing methodology of embedded DRAMs
Hao Yu Yang
*
, Chi Min Chang
,
Chia-Tso Chao
, Rei Fu Huang
, Shih Chin Lin
*
Corresponding author for this work
Research output
:
Contribution to journal
›
Article
›
peer-review
24
Scopus citations
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Engineering
Experimental Result
100%
Test Time
100%
Error Correction
100%
Correction Code
100%
Mathematical Model
100%
Keyphrases
Testing Method
100%
EDRAM
100%
DRAM Testing
42%
Wafer
14%
Mathematical Model
14%
Circuitry
14%
High Temperature
14%
Fault Coverage
14%
Leakage Mechanism
14%
Defect Levels
14%
DRAM Cell
14%
Testing Algorithm
14%
Wearout
14%
Error Correction Codes
14%
SRAM Architecture
14%
Special Functions
14%
Switching Transistor
14%
1T-SRAM
14%
Computer Science
Experimental Result
100%
Fault Coverage
100%
Test Algorithm
100%
Error Correction Code
100%
Mathematics
Mathematical Modeling
100%
Error Correction
100%
Special Function
100%