Testing Methodology of Embedded DRAMs

Chi Min Chang*, Chia-Tso Chao, Rei Fu Huangt, Ding Yuan Chen

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations


    The embedded-DRAMtesting mixes up the techniques used for DRAM testing and SRAM testing since an embedded- DRAM core combines DRAM cells with an SRAM interface (the so-called 1 T-SRAM architecture). In this paper, we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Theexperimental results are collected based on 1-lot wafers with an 16Mb embedded DRAM core.

    Original languageEnglish
    Title of host publicationProceedings - International Test Conference 2008, ITC 2008
    StatePublished - 2008
    EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
    Duration: 28 Oct 200830 Oct 2008

    Publication series

    NameProceedings - International Test Conference
    ISSN (Print)1089-3539


    ConferenceInternational Test Conference 2008, ITC 2008
    Country/TerritoryUnited States
    CitySanta Clara, CA


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