TY - GEN
T1 - Testing Algorithm Parameter and Device Area Effect in HfO2OX-RRAM
AU - Chen, Ching Hua
AU - Ma, Chi Yuan
AU - Yang, Chen Ghan
AU - Lai, Han Chao
AU - Kang, Chiu Ching
AU - Wu, Pu Wei
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - We demonstrated an optimization procedure of SET and RESET parameters in HfO2-based resistive random-access memory (OX-RRAM). The vertical layout for the OX-RRAM is TiN/AlOxTiOx/TiN (top electrode/top interfacial layer/insulator/bottom interfacial layer/bottom electrode). There are four parameters that could decide the four performances of OX-RRAM, which are compliance current, interval operation voltage, maximum interval voltage and device area. The OX-RRAM device performances are compared with resistance ratio (RRESET/RSET) and endurance. From the power consumption, resistance ratio and resistance endurance, we suggested a methodology of interval voltage optimization instead of compliance current in our OX-RRAM. After optimization, interval voltage 0.125 volts, maximum interval 4.0 volts with 10×10μm2 providing 2.22.4 resistance ratio (RRESET/RSET) with over 200 cycles was applied. The 10×10μm2 has higher resistance ratio (RRESET/RsET) 2.2,_,2.4 with 200 cycle. However, 35×35 μm2 could also sustain 255 cycles with 0.81.2 resistance ratio (RRESET/RSET). The flexibility of device area could provide different resistance ratio and endurance combination, where no further voltage or current optimization is needed. The smaller area OX-RRAM could apply as 'buffer' memory, which requires small device area with placement flexibility. The larger area OX-RRAM with longer endurance could apply as 'storage' memory, which requires robust endurance under higher operating frequency.
AB - We demonstrated an optimization procedure of SET and RESET parameters in HfO2-based resistive random-access memory (OX-RRAM). The vertical layout for the OX-RRAM is TiN/AlOxTiOx/TiN (top electrode/top interfacial layer/insulator/bottom interfacial layer/bottom electrode). There are four parameters that could decide the four performances of OX-RRAM, which are compliance current, interval operation voltage, maximum interval voltage and device area. The OX-RRAM device performances are compared with resistance ratio (RRESET/RSET) and endurance. From the power consumption, resistance ratio and resistance endurance, we suggested a methodology of interval voltage optimization instead of compliance current in our OX-RRAM. After optimization, interval voltage 0.125 volts, maximum interval 4.0 volts with 10×10μm2 providing 2.22.4 resistance ratio (RRESET/RSET) with over 200 cycles was applied. The 10×10μm2 has higher resistance ratio (RRESET/RsET) 2.2,_,2.4 with 200 cycle. However, 35×35 μm2 could also sustain 255 cycles with 0.81.2 resistance ratio (RRESET/RSET). The flexibility of device area could provide different resistance ratio and endurance combination, where no further voltage or current optimization is needed. The smaller area OX-RRAM could apply as 'buffer' memory, which requires small device area with placement flexibility. The larger area OX-RRAM with longer endurance could apply as 'storage' memory, which requires robust endurance under higher operating frequency.
KW - Bipolar resistive RAM
KW - compliance current
KW - duration time
KW - HfO
KW - interval voltage
UR - http://www.scopus.com/inward/record.url?scp=85126224520&partnerID=8YFLogxK
U2 - 10.1109/IMPACT53160.2021.9696885
DO - 10.1109/IMPACT53160.2021.9696885
M3 - Conference contribution
AN - SCOPUS:85126224520
T3 - Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
SP - 215
EP - 221
BT - 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2021 - Proceedings
PB - IEEE Computer Society
T2 - 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2021
Y2 - 21 December 2021 through 23 December 2021
ER -