Testability considerations

Shang Zhi Sun; David H.C. Du; Duen-Ren Liu

doi:10.1109/ICCD.1994.331863

Testability considerations

Shang Zhi Sun^*, David H.C. Du, Duen-Ren Liu

^*Corresponding author for this work

Institute of Information Management

Research output: Contribution to conference › Paper › peer-review

Abstract

Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D_1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

Original language	English
Pages	97-100
Number of pages	4
DOIs	https://doi.org/10.1109/ICCD.1994.331863
State	Published - 1994
Event	Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: 10 Oct 1994 → 12 Oct 1994

Conference

Conference	Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
City	Cambridge, MA, USA
Period	10/10/94 → 12/10/94

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10.1109/ICCD.1994.331863

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title = "Testability considerations",

abstract = "Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?",

author = "Sun, {Shang Zhi} and Du, {David H.C.} and Duen-Ren Liu",

year = "1994",

doi = "10.1109/ICCD.1994.331863",

language = "English",

pages = "97--100",

note = "Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors ; Conference date: 10-10-1994 Through 12-10-1994",

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N2 - Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

AB - Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?

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Y2 - 10 October 1994 through 12 October 1994

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Testability considerations

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