Test Structures to Investigate ESD Robustness of Integrated GaN Devices

Wei Cheng Wang, Ming Dou Ker*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

When more circuit functions are integrated into a single chip fabricated by GaN-on-Silicon process, the on-chip electrostatic discharge (ESD) protection design shall be provided to protect the GaN integrated circuits. In this work, ESD robustness of E-HEMT GaN devices was investigated through test structures that fabricated in a GaN-on-Silicon process. The experimental results showed that the ESD robustness is proportional to the device dimension when the GaN device was operating in the forward mode. In addition, with the gate-coupled design, the ESD level of E-HEMT GaN device can be further improved. Based on the investigation results of this work, the whole-chip ESD protection scheme can be successfully realized by E-HEMT GaN devices.

Original languageEnglish
Title of host publication2024 IEEE 36th International Conference on Microelectronic Test Structures, ICMTS 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350329896
DOIs
StatePublished - 2024
Event36th IEEE International Conference on Microelectronic Test Structures, ICMTS 2024 - Edinburgh, United Kingdom
Duration: 15 Apr 202418 Apr 2024

Publication series

NameIEEE International Conference on Microelectronic Test Structures
ISSN (Print)1071-9032
ISSN (Electronic)2158-1029

Conference

Conference36th IEEE International Conference on Microelectronic Test Structures, ICMTS 2024
Country/TerritoryUnited Kingdom
CityEdinburgh
Period15/04/2418/04/24

Keywords

  • E-HEMT
  • Electrostatic discharge (ESD)
  • GaN
  • human body model (HBM)
  • transmission line pulse (TLP)

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