TY - GEN
T1 - Test structure on SCR device in waffle layout for RF ESD protection
AU - Ker, Ming-Dou
AU - Lin, Chun Yu
PY - 2007/9/27
Y1 - 2007/9/27
N2 - With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.
AB - With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.
KW - Electrostatic discharges (ESD)
KW - Radio-frequency integrated circuit (RF IC)
KW - Silicon-controlled rectifier (SCR)
UR - http://www.scopus.com/inward/record.url?scp=34548828536&partnerID=8YFLogxK
U2 - 10.1109/ICMTS.2007.374482
DO - 10.1109/ICMTS.2007.374482
M3 - Conference contribution
AN - SCOPUS:34548828536
SN - 142440780X
SN - 9781424407804
T3 - IEEE International Conference on Microelectronic Test Structures
SP - 196
EP - 199
BT - 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
T2 - 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
Y2 - 19 March 2007 through 22 March 2007
ER -