Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker; Jeng Jie Peng; Hsin Chin Jiang

doi:10.1109/ICMTS.2003.1197455

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker^*, Jeng Jie Peng, Hsin Chin Jiang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

Original language	English
Pages	161-166
Number of pages	6
DOIs	https://doi.org/10.1109/ICMTS.2003.1197455
State	Published - Mar 2003
Event	IEEE International Conference on Microelectronic Test Structures - Monterey, CA, United States Duration: 17 Mar 2003 → 20 Mar 2003

Conference

Conference	IEEE International Conference on Microelectronic Test Structures
Country/Territory	United States
City	Monterey, CA
Period	17/03/03 → 20/03/03

Access to Document

10.1109/ICMTS.2003.1197455

Cite this

@conference{0b4186b34e664443af2b0b3c61981b1e,

title = "Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's",

abstract = "For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.",

author = "Ming-Dou Ker and Peng, {Jeng Jie} and Jiang, {Hsin Chin}",

year = "2003",

month = mar,

doi = "10.1109/ICMTS.2003.1197455",

language = "English",

pages = "161--166",

note = "IEEE International Conference on Microelectronic Test Structures ; Conference date: 17-03-2003 Through 20-03-2003",

}

TY - CONF

T1 - Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

AU - Ker, Ming-Dou

AU - Peng, Jeng Jie

AU - Jiang, Hsin Chin

PY - 2003/3

Y1 - 2003/3

N2 - For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

AB - For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

UR - http://www.scopus.com/inward/record.url?scp=0037628043&partnerID=8YFLogxK

U2 - 10.1109/ICMTS.2003.1197455

DO - 10.1109/ICMTS.2003.1197455

M3 - Paper

AN - SCOPUS:0037628043

SP - 161

EP - 166

T2 - IEEE International Conference on Microelectronic Test Structures

Y2 - 17 March 2003 through 20 March 2003

ER -

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this