Test Methodology for Defect-Based Bridge Faults

Shuo Wen Chang, Yu Teng Nien, Yu Pang Hu, Kai Chiang Wu, Chi Chun Wang, Fu Sheng Huang, Yi Lun Tang, Yung Chen Chen, Ming Chien Chen, Mango C.T. Chao

Research output: Contribution to journalArticlepeer-review


A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE simulating the two shorted cells with the short defect injected. In this article, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial automatic test pattern generation (ATPG) to generate corresponding test patterns for a given design. A defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using a defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared with a conventional four-way dominance bridge fault model, where four noncollapsible faults at one shorted cell pair are considered for ATPG. In addition, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for four-way dominance bridge faults with more test patterns. The runtime required for extracting 1-time-frame (1tf) defect-based bridge faults has been proven acceptable on industrial designs and some techniques were also proposed to speed up the runtime for extracting 2tf defect-based bridge faults. All experiments in this article are conducted based on industrial designs.


  • Automatic test pattern generation (ATPG)
  • Bridge circuits
  • bridge defect
  • Bridges
  • Circuit faults
  • circuit faults
  • critical area
  • defect-based test
  • delays
  • integrated circuit interconnections
  • Integrated circuit interconnections
  • layout
  • logic testing
  • Metals
  • Resistance
  • Runtime
  • SPICE.


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