Test Generation for Defect-Based Faults of Scan Flip-Flops

Yu Teng Nien, Chen Hong Li, Pei Yin Wu, Yung Jheng Wang, Kai Chiang Wu, Mango C.T. Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

When testing scan flip-flops (SFFs), chain test is first applied to ensure the functionality of scan chains and to detect the majority of stuck-at (SA) and transition delay (TD) faults along scan paths. However, there still exist some defects inside scan cells that cannot be effectively detected by chain test or conventional SA and TD patterns. This paper presents five cell-aware (CA) fault models to explicitly target the defects inside scan flip-flops. The proposed static shift (SS) and dynamic shift (DS) faults identify the defects detectable by chain test. For the defects escaping chain test, static single-capture (SSC) faults target the defects detectable when SFFs are in one-cycle capture mode, while static double-capture (SDC) and dynamic double-capture (DDC) faults target those detectable when SFFs are in two-cycle capture mode. The identified CA faults of SFFs are output in a format compatible with a commercial ATPG tool for pattern generation. Experimental results on large IWLS05 benchmarks demonstrate that our proposed faults cannot be fully covered by conventional SA and TD patterns and hence require dedicated test patterns to detect.

Original languageEnglish
Title of host publicationProceedings - 2023 IEEE 41st VLSI Test Symposium, VTS 2023
PublisherIEEE Computer Society
ISBN (Electronic)9798350346305
DOIs
StatePublished - 2023
Event41st IEEE VLSI Test Symposium, VTS 2023 - San Diego, United States
Duration: 24 Apr 202326 Apr 2023

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2023-April

Conference

Conference41st IEEE VLSI Test Symposium, VTS 2023
Country/TerritoryUnited States
CitySan Diego
Period24/04/2326/04/23

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