Test generation and site of fault for combinational circuits using logic Petri Nets

Jui I. Tsai*, Ching Cheng Teng, Ching Hung Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose a novel Petri Net model for solving test generation and site of fault and fired logical value for combinational circuits. In order to improve the logic fault efficiency, the transitions of general Petri Nets (PNs) are modified according to the critical of truth table, called Logic Petri Net LPN. The LPN model can transfer complexity circuit problem to a local adjacent place and transition relational problem. Therefore, the site of fault and fired logical value problem is simplified and clearly. The LPN model has the properties of Boolean algorithm, collapsing fault with clear physical concepts, fast calculation speed, and high veracity. The approach contains site of a fault and fired logical value reasoning algorithm and test vector generation reasoning algorithm. Two examples are shown to demonstrate the effectiveness of our approach.

Original languageEnglish
Title of host publication2006 IEEE International Conference on Systems, Man and Cybernetics
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages91-96
Number of pages6
ISBN (Print)1424401003, 9781424401000
DOIs
StatePublished - 2006
Event2006 IEEE International Conference on Systems, Man and Cybernetics - Taipei, Taiwan
Duration: 8 Oct 200611 Oct 2006

Publication series

NameConference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
Volume1
ISSN (Print)1062-922X

Conference

Conference2006 IEEE International Conference on Systems, Man and Cybernetics
Country/TerritoryTaiwan
CityTaipei
Period8/10/0611/10/06

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