Tendency for full depletion due to gate tunneling current

Hui Wan; Samuel K H Fung; Pin Su; Mansun Chan; Chen-Ming Hu

doi:10.1109/SOI.2002.1044452

Tendency for full depletion due to gate tunneling current

Hui Wan^*, Samuel K H Fung, Pin Su, Mansun Chan, Chen-Ming Hu

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

6 Scopus citations

Abstract

High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with V_g=- V_dd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.

Original language	English
Pages	140-142
Number of pages	3
DOIs	https://doi.org/10.1109/SOI.2002.1044452
State	Published - 2002
Event	IEEE International SOI Conference - Williamsburg, VA, United States Duration: 7 Oct 2002 → 10 Oct 2002

Conference

Conference	IEEE International SOI Conference
Country/Territory	United States
City	Williamsburg, VA
Period	7/10/02 → 10/10/02

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10.1109/SOI.2002.1044452

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title = "Tendency for full depletion due to gate tunneling current",

abstract = "High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg=- Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.",

author = "Hui Wan and Fung, {Samuel K H} and Pin Su and Mansun Chan and Chen-Ming Hu",

year = "2002",

doi = "10.1109/SOI.2002.1044452",

language = "English",

pages = "140--142",

note = "IEEE International SOI Conference ; Conference date: 07-10-2002 Through 10-10-2002",

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TY - CONF

T1 - Tendency for full depletion due to gate tunneling current

AU - Wan, Hui

AU - Fung, Samuel K H

AU - Su, Pin

AU - Chan, Mansun

AU - Hu, Chen-Ming

PY - 2002

Y1 - 2002

N2 - High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg=- Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.

AB - High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg=- Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=0036454483&partnerID=8YFLogxK

U2 - 10.1109/SOI.2002.1044452

DO - 10.1109/SOI.2002.1044452

M3 - Paper

AN - SCOPUS:0036454483

SP - 140

EP - 142

T2 - IEEE International SOI Conference

Y2 - 7 October 2002 through 10 October 2002

ER -

Tendency for full depletion due to gate tunneling current

Abstract

Conference

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