Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for Cold Electronics

We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature of 77 K-300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage ( V_{mathrm{ th}} ) increase and subthreshold swing (SS) reduction than N-MOSFETs, whereas the improvement in drain-induced barrier lowering (DIBL) is more evident in N-MOSFETs. N-MOSFETs show typical reverse narrow effect (RNWEs) in terms of V_{mathrm{ th}} roll-off along with SS rise-up with narrowing channel-widths ( W_{mathrm{ G}} ). In contrast, P-MOSFETs exhibit anomalous RNWE, that is, V_{mathrm{ th}} (SS) decreases (increases) with decreasing W_{mathrm{ G}} from 3 mu text{m} to 0.6 mu text{m} and reversely increases (decreases) with further narrowing to 0.3 mu text{m}. RNWEs on N-MOSFETs are clearly suppressed at cryogenic temperatures, whereas P-MOSFETs appear to have enhanced anomalous RNWEs in terms of V_{mathrm{ th}} and DIBL variations at 77 K.