Technology, performance, and computer-aided design of three-dimensional integrated circuits

Shamik Das*, Chuan Seng Tan, Andy Fan, Nisha Checka, Kuan-Neng Chen, Rafael Reif

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    102 Scopus citations

    Abstract

    We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3-D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3-D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3-D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

    Original languageEnglish
    Pages108-115
    Number of pages8
    DOIs
    StatePublished - Apr 2004
    EventProceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, United States
    Duration: 18 Apr 200421 Apr 2004

    Conference

    ConferenceProceedings of the International Symposium on Physical Design, ISPD 2004
    Country/TerritoryUnited States
    CityPhoenix, AZ
    Period18/04/0421/04/04

    Keywords

    • 3-D IC
    • 3-D VLSI
    • 3-D integration
    • Layout
    • Placement
    • Routing

    Fingerprint

    Dive into the research topics of 'Technology, performance, and computer-aided design of three-dimensional integrated circuits'. Together they form a unique fingerprint.

    Cite this