Technology and applications of three-dimensional integration

Rafael Reif*, Chuan Seng Tan, Andy Fan, Kuan-Neng Chen, Shamik Das, Nisha Checka

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    3 Scopus citations

    Abstract

    Three-dimensional (3-D) integration holds tremendous potential to reduce global interconnect latency and power dissipation, and to improve integrated circuits (ICs) form factor. Moreover, it allows heterogeneous integration of different functional blocks (e.g., logic, memory, RF, etc) and materials (e.g., Silicon, SiGe, III-IV, etc). This paper explores the opportunities and challenges of a 3-D integration approach based on a silicon layer transfer process. It combines low temperature direct wafer bonding (Cu-to-Cu and SiO 2-to-SiO 2), high rate and selectivity silicon etching, and wafer de-bonding. A thorough description, of process integration will be given and key technological challenges will be highlighted. In addition, CAD tools for 3-D ICs design and layout are being developed. Potential 3-D applications for system-on-a-chip (SoC) and related issues will be discussed.

    Original languageEnglish
    Pages261-276
    Number of pages16
    StatePublished - Oct 2004
    EventDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States
    Duration: 3 Oct 20048 Oct 2004

    Conference

    ConferenceDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
    Country/TerritoryUnited States
    CityHonolulu, HI
    Period3/10/048/10/04

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