Abstract
A survey is presented of three techniques for the trace-driven simulation of cache designs: stack analysis methodologies that make it possible to obtain performance measures for a wide variety of cache designs from a single run of the simulator, compression algorithms specifically tailored to memory reference traces, and an approach to parallel trace-driven simulation of multiprocessor caches that dramatically reduces the simulation's synchronization and thus its running time.
| Original language | English |
|---|---|
| Pages (from-to) | 1042-1046 |
| Number of pages | 5 |
| Journal | Winter Simulation Conference Proceedings |
| DOIs | |
| State | Published - 1 Dec 1989 |
| Event | 1989 Winter Simulation Conference Proceedings - WSC '89 - Washington, DC, USA Duration: 4 Dec 1989 → 6 Dec 1989 |
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