Tailoring a parallel trace-driven simulation technique to specific multiprocessor cache coherence protocols

This paper concerns the design and analysis of parallel algorithms for the trace-driven simulation of multiprocessor cache coherence protocols. Simulations are often used in computer system design. Since simulations are time-consuming, it is natural to attempt to use parallel computing to accelerate them. In a previous paper we devised and analyzed a general technique for the parallel trace-driven simulation of multiprocessor cache coherence protocols. In this paper we optimize our general technique to simulate various specific protocols. The surprising result is that using our technique, the processes simulating the caches often need to do little or no communication even when simulating shared references. Thus, linear or near-linear speedup is possible.