Systolic building block for logic-on-logic 3D-IC implementations of convolutional neural networks

H. T. Kung, Bradley McDanel, Sai Qian Zhang, C. T. Wang, Jin Cai, C. Y. Chen, Victor C.Y. Chang, M. F. Chen, Jack Y.C. Sun, Douglas Yu

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Abstract

    We present a building block architecture for systolic array 3D-IC implementations of convolutional neural network (CNN) inference. The building block can be part of a library offered by a chip design service provider to support efficient CNN implementations. We describe how the building block can form systolic arrays for implementing low-latency, energy-efficient CNN inference for models of any size, while incorporating advanced packaging features such as “logic-on-logic” 3D-IC (micro-bump/TSV, monolithic 3D or other 3D technology). We present delay and power analysis for 2D and 3D implementations, and argue that as systolic arrays scale in size, 3D implementations based on, e.g., micro-bump/TSV, lead to significant performance improvements over 2D implementations.

    Original languageEnglish
    Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781728103976
    DOIs
    StatePublished - 2019
    Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
    Duration: 26 May 201929 May 2019

    Publication series

    NameProceedings - IEEE International Symposium on Circuits and Systems
    Volume2019-May
    ISSN (Print)0271-4310

    Conference

    Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
    Country/TerritoryJapan
    CitySapporo
    Period26/05/1929/05/19

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