System-on-a-chip design of a low-power smart vision system

Wai-Chi  Fang

doi:10.1109/SIPS.1998.715769

System-on-a-chip design of a low-power smart vision system

Wai-Chi Fang^*

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

A low power smart imager design is proposed for real time machine vision applications. It takes advantages of recent advances in integrated sensing/processing designs, electronic neural networks, and sub-micron VLSI technology. The smart vision system integrates an active pixel camera with a programmable neural computer and an advanced microcomputer. A system-on-a-chip implementation of this smart vision system is shown to be feasible by integrating the whole system into a 3-cm×3-cm chip design in a 0.18 m CMOS technology. The on-chip neural computer provides one tera-operation-per-second computing power for various parallel vision operations and smart sensor functions. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and system-on-a-chip implementation. This highly integrated smart imager can be used for various scientific missions and other military, industrial or commercial vision applications.

Original language	English
Pages	63-72
Number of pages	10
DOIs	https://doi.org/10.1109/SIPS.1998.715769
State	Published - 1 Jan 1998
Event	Proceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS - Cambridge, MA, USA Duration: 8 Oct 1998 → 10 Oct 1998

Conference

Conference	Proceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS
City	Cambridge, MA, USA
Period	8/10/98 → 10/10/98

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10.1109/SIPS.1998.715769

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abstract = "A low power smart imager design is proposed for real time machine vision applications. It takes advantages of recent advances in integrated sensing/processing designs, electronic neural networks, and sub-micron VLSI technology. The smart vision system integrates an active pixel camera with a programmable neural computer and an advanced microcomputer. A system-on-a-chip implementation of this smart vision system is shown to be feasible by integrating the whole system into a 3-cm×3-cm chip design in a 0.18 m CMOS technology. The on-chip neural computer provides one tera-operation-per-second computing power for various parallel vision operations and smart sensor functions. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and system-on-a-chip implementation. This highly integrated smart imager can be used for various scientific missions and other military, industrial or commercial vision applications.",

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AB - A low power smart imager design is proposed for real time machine vision applications. It takes advantages of recent advances in integrated sensing/processing designs, electronic neural networks, and sub-micron VLSI technology. The smart vision system integrates an active pixel camera with a programmable neural computer and an advanced microcomputer. A system-on-a-chip implementation of this smart vision system is shown to be feasible by integrating the whole system into a 3-cm×3-cm chip design in a 0.18 m CMOS technology. The on-chip neural computer provides one tera-operation-per-second computing power for various parallel vision operations and smart sensor functions. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and system-on-a-chip implementation. This highly integrated smart imager can be used for various scientific missions and other military, industrial or commercial vision applications.

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System-on-a-chip design of a low-power smart vision system

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