Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET

Yun Yan Chung; Chao Ching Cheng; Bo Kai Kang; Wei Chen Chueh; Shih Yun Wang; Chen Han Chou; Terry Y.T. Hung; Shin Yuan Wang; Wen Hao Chang; Lain Jong Li; Chao Hsin Chien

doi:10.1109/IEDM13553.2020.9372072

Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET

Yun Yan Chung, Chao Ching Cheng^*, Bo Kai Kang, Wei Chen Chueh, Shih Yun Wang, Chen Han Chou, Terry Y.T. Hung, Shin Yuan Wang, Wen Hao Chang, Lain Jong Li, Chao Hsin Chien

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

Original language	English
Title of host publication	2020 IEEE International Electron Devices Meeting, IEDM 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	40.3.1-40.3.4
ISBN (Electronic)	9781728188881
DOIs	https://doi.org/10.1109/IEDM13553.2020.9372072
State	Published - 12 Dec 2020
Event	66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States Duration: 12 Dec 2020 → 18 Dec 2020

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2020-December
ISSN (Print)	0163-1918

Conference

Conference	66th Annual IEEE International Electron Devices Meeting, IEDM 2020
Country/Territory	United States
City	Virtual, San Francisco
Period	12/12/20 → 18/12/20

Access to Document

10.1109/IEDM13553.2020.9372072

Cite this

Chung, Y. Y., Cheng, C. C., Kang, B. K., Chueh, W. C., Wang, S. Y., Chou, C. H., Hung, T. Y. T., Wang, S. Y., Chang, W. H., Li, L. J., & Chien, C. H. (2020). Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. In 2020 IEEE International Electron Devices Meeting, IEDM 2020 (pp. 40.3.1-40.3.4). [9372072] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2020-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM13553.2020.9372072

@inproceedings{df01314556cb4708a6fbb8e92c697619,

title = "Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET",

abstract = "We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.",

author = "Chung, {Yun Yan} and Cheng, {Chao Ching} and Kang, {Bo Kai} and Chueh, {Wei Chen} and Wang, {Shih Yun} and Chou, {Chen Han} and Hung, {Terry Y.T.} and Wang, {Shin Yuan} and Chang, {Wen Hao} and Li, {Lain Jong} and Chien, {Chao Hsin}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; null ; Conference date: 12-12-2020 Through 18-12-2020",

year = "2020",

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doi = "10.1109/IEDM13553.2020.9372072",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Chung, YY, Cheng, CC, Kang, BK, Chueh, WC, Wang, SY, Chou, CH, Hung, TYT, Wang, SY, Chang, WH, Li, LJ & Chien, CH 2020, Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. in 2020 IEEE International Electron Devices Meeting, IEDM 2020., 9372072, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2020-December, Institute of Electrical and Electronics Engineers Inc., pp. 40.3.1-40.3.4, 66th Annual IEEE International Electron Devices Meeting, IEDM 2020, Virtual, San Francisco, United States, 12/12/20. https://doi.org/10.1109/IEDM13553.2020.9372072

Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. / Chung, Yun Yan; Cheng, Chao Ching; Kang, Bo Kai et al.

2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 40.3.1-40.3.4 9372072 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2020-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chung, Yun Yan

AU - Cheng, Chao Ching

AU - Kang, Bo Kai

AU - Chueh, Wei Chen

AU - Wang, Shih Yun

AU - Chou, Chen Han

AU - Hung, Terry Y.T.

AU - Wang, Shin Yuan

AU - Chang, Wen Hao

AU - Li, Lain Jong

AU - Chien, Chao Hsin

PY - 2020/12/12

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N2 - We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

AB - We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

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Chung YY, Cheng CC, Kang BK, Chueh WC, Wang SY, Chou CH et al. Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. In 2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 40.3.1-40.3.4. 9372072. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM13553.2020.9372072