Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si

Chia Chen Wan, Guang Li Luo, Shu Han Hsu, Kuo Dong Hung, Chun Lin Chu, Tuo-Hung Hou, Chun Jun Su, Szu Hung Chen, Wen Fa Wu, Wen Kuan Yeh

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility 111 surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I ON /I OFF ) of 5×10 5 , which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.

    Original languageEnglish
    Title of host publication2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages130-131
    Number of pages2
    ISBN (Electronic)9781509007264
    DOIs
    StatePublished - 13 Jun 2016
    Event21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States
    Duration: 12 Jun 201613 Jun 2016

    Publication series

    Name2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

    Conference

    Conference21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
    Country/TerritoryUnited States
    CityHonolulu
    Period12/06/1613/06/16

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