Surge protection design with surge-to-digital converter for microelectronic circuits and systems

Wen Chieh Chen; Ming-Dou Ker

doi:10.1016/j.microrel.2018.06.087

Surge protection design with surge-to-digital converter for microelectronic circuits and systems

Wen Chieh Chen, Ming-Dou Ker^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of V_DD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

Original language	English
Pages (from-to)	2-5
Number of pages	4
Journal	Microelectronics Reliability
Volume	88-90
DOIs	https://doi.org/10.1016/j.microrel.2018.06.087
State	Published - 1 Sep 2018

Keywords

Electrical overstress (EOS)
Surge
Surge detection
Surge protection
Surge-to-digital converter

Access to Document

10.1016/j.microrel.2018.06.087

Cite this

@article{718df0818b4c496fa806ea5c99961d6c,

title = "Surge protection design with surge-to-digital converter for microelectronic circuits and systems",

abstract = "A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.",

keywords = "Electrical overstress (EOS), Surge, Surge detection, Surge protection, Surge-to-digital converter",

author = "Chen, {Wen Chieh} and Ming-Dou Ker",

year = "2018",

month = sep,

day = "1",

doi = "10.1016/j.microrel.2018.06.087",

language = "English",

volume = "88-90",

pages = "2--5",

journal = "Microelectronics Reliability",

issn = "0026-2714",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - Surge protection design with surge-to-digital converter for microelectronic circuits and systems

AU - Chen, Wen Chieh

AU - Ker, Ming-Dou

PY - 2018/9/1

Y1 - 2018/9/1

N2 - A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

AB - A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

KW - Electrical overstress (EOS)

KW - Surge

KW - Surge detection

KW - Surge protection

KW - Surge-to-digital converter

UR - http://www.scopus.com/inward/record.url?scp=85054785057&partnerID=8YFLogxK

U2 - 10.1016/j.microrel.2018.06.087

DO - 10.1016/j.microrel.2018.06.087

M3 - Article

AN - SCOPUS:85054785057

SN - 0026-2714

VL - 88-90

SP - 2

EP - 5

JO - Microelectronics Reliability

JF - Microelectronics Reliability

ER -

Surge protection design with surge-to-digital converter for microelectronic circuits and systems

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this