Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate

Ray-Hua Horng; W. C. Peng; D. S. Wuu; W. J. Ho; Y. S. Huang

doi:10.1016/S0038-1101(02)00049-7

Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate

Ray-Hua Horng^*, W. C. Peng, D. S. Wuu, W. J. Ho, Y. S. Huang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

We have investigated the surface morphology and electrical properties of directly wafer-bonded GaAs and InP by surface treatment and fusion annealed temperatures. The surface morphologies of bond samples with and without pattern under uniaxial pressure with thermal treatment in N₂ ambient were compared. It was found that the peeling, bubbles and cracks have almost completely eliminated and high quality fusion surface area of 2 cm × 2 cm can be obtained using the pattern with 3000 μm pitch and 10 μm width channel. Bonded interfaces were also characterized by transmission electron microscopy and revealed that neither threading dislocation nor stacking fault. The current-voltage characteristics have also been demonstrated to be results from different wafer cleaning processes and bonding at various temperatures. Using the H₂SO₄:H₂O₂:H₂O and dilute HF etching solution, the free barrier interface of n-InP (2 × 10¹⁹ cm^-3) bonded to n-GaAs (1 × 10¹⁸ cm^-3) at 550 °C can be obtained.

Original language	English
Pages (from-to)	1103-1108
Number of pages	6
Journal	Solid-State Electronics
Volume	46
Issue number	8
DOIs	https://doi.org/10.1016/S0038-1101(02)00049-7
State	Published - 1 Aug 2002

Keywords

Directly wafer bonded
Free barrier interface
Surface treatment

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10.1016/S0038-1101(02)00049-7

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title = "Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate",

abstract = "We have investigated the surface morphology and electrical properties of directly wafer-bonded GaAs and InP by surface treatment and fusion annealed temperatures. The surface morphologies of bond samples with and without pattern under uniaxial pressure with thermal treatment in N2 ambient were compared. It was found that the peeling, bubbles and cracks have almost completely eliminated and high quality fusion surface area of 2 cm × 2 cm can be obtained using the pattern with 3000 μm pitch and 10 μm width channel. Bonded interfaces were also characterized by transmission electron microscopy and revealed that neither threading dislocation nor stacking fault. The current-voltage characteristics have also been demonstrated to be results from different wafer cleaning processes and bonding at various temperatures. Using the H2SO4:H2O2:H2O and dilute HF etching solution, the free barrier interface of n-InP (2 × 1019 cm-3) bonded to n-GaAs (1 × 1018 cm-3) at 550 °C can be obtained.",

keywords = "Directly wafer bonded, Free barrier interface, Surface treatment",

author = "Ray-Hua Horng and Peng, {W. C.} and Wuu, {D. S.} and Ho, {W. J.} and Huang, {Y. S.}",

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T1 - Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate

AU - Horng, Ray-Hua

AU - Peng, W. C.

AU - Wuu, D. S.

AU - Ho, W. J.

AU - Huang, Y. S.

PY - 2002/8/1

Y1 - 2002/8/1

N2 - We have investigated the surface morphology and electrical properties of directly wafer-bonded GaAs and InP by surface treatment and fusion annealed temperatures. The surface morphologies of bond samples with and without pattern under uniaxial pressure with thermal treatment in N2 ambient were compared. It was found that the peeling, bubbles and cracks have almost completely eliminated and high quality fusion surface area of 2 cm × 2 cm can be obtained using the pattern with 3000 μm pitch and 10 μm width channel. Bonded interfaces were also characterized by transmission electron microscopy and revealed that neither threading dislocation nor stacking fault. The current-voltage characteristics have also been demonstrated to be results from different wafer cleaning processes and bonding at various temperatures. Using the H2SO4:H2O2:H2O and dilute HF etching solution, the free barrier interface of n-InP (2 × 1019 cm-3) bonded to n-GaAs (1 × 1018 cm-3) at 550 °C can be obtained.

AB - We have investigated the surface morphology and electrical properties of directly wafer-bonded GaAs and InP by surface treatment and fusion annealed temperatures. The surface morphologies of bond samples with and without pattern under uniaxial pressure with thermal treatment in N2 ambient were compared. It was found that the peeling, bubbles and cracks have almost completely eliminated and high quality fusion surface area of 2 cm × 2 cm can be obtained using the pattern with 3000 μm pitch and 10 μm width channel. Bonded interfaces were also characterized by transmission electron microscopy and revealed that neither threading dislocation nor stacking fault. The current-voltage characteristics have also been demonstrated to be results from different wafer cleaning processes and bonding at various temperatures. Using the H2SO4:H2O2:H2O and dilute HF etching solution, the free barrier interface of n-InP (2 × 1019 cm-3) bonded to n-GaAs (1 × 1018 cm-3) at 550 °C can be obtained.

KW - Directly wafer bonded

KW - Free barrier interface

KW - Surface treatment

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DO - 10.1016/S0038-1101(02)00049-7

M3 - Article

AN - SCOPUS:0036680656

SN - 0038-1101

VL - 46

SP - 1103

EP - 1108

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 8

ER -

Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate

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Keywords

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