Surface characteristics optimization during wafer-level backside silicon removal for SOI wafers in 3D integration

This study highlights an innovative technique to optimize surface characteristics for backside silicon removal in three-dimensional (3D) integration. Following the grinding process, the silicon wafer exhibits subsurface damage and elevated surface roughness, necessitating effective post-processing strategies. By applying chemical mechanical polishing (CMP) with a controlled pressure, significant surface planarization is achieved, resulting in a reduction in roughness from 1 μm to 0.4 nm. Furthermore, the hydrofluoric-nitric acid (HNA) treatment efficiently removes non-(100) silicon layers, restoring the surface characteristics and ensuring optimal etching conditions for subsequent tetramethylammonium hydroxide (TMAH) anisotropic wet etching. Subsequently, etching efficiency was improved by implementing a TMAH/dilute hydrofluoric acid (DHF) cycle, which facilitated the complete removal of the backside silicon and resulted in the formation of a transparent, ultra-thin interlayer. Verification through focused ion beam (FIB) milling and X-ray photoelectron spectroscopy (XPS) confirms the successful exposure of the buried oxide layer, underscoring the effectiveness of this approach in advancing 3D integration technologies.