Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

Shu Han Whi*, Yu-Min Lee

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

    Original languageEnglish
    Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Pages418-421
    Number of pages4
    DOIs
    StatePublished - 28 Jun 2011
    Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
    Duration: 25 Apr 201128 Apr 2011

    Publication series

    NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    Conference

    Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Country/TerritoryTaiwan
    CityHsinchu
    Period25/04/1128/04/11

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