Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs

Meng Fan Chang*, Kuei-Ann Wen, Ding Ming Kwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

Pattern-sensitive soft errors, subject to varied supply and substrate noises, have become increasingly significant for configurable memories embedded in SoCs. In this paper, we study their effects on memory cell, array, and circuit design. It is found that the ground bounce reduces the cell current more severely than the supply voltage drop and substrate bias dip. This encourages the use of metal wires along the wordline or row direction. Bitline tracking by current ratio achieves better accuracy and design for manufacturing (DFM) capability than by capacitance ratio. It requires further enhancement to be resilient to the supply and substrate noises. The proposed dynamic tracking cluster technique provides necessary timing relaxation, while minimizing the speed degradation. Configurable embedded SRAM and ROM in 0.18μm CMOS process are studied.

Original languageEnglish
Title of host publicationProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
PublisherIEEE Computer Society
Pages297-302
Number of pages6
ISBN (Print)0769520936, 9780769520933
DOIs
StatePublished - 1 Jan 2004
EventProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States
Duration: 22 Mar 200424 Mar 2004

Publication series

NameProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Conference

ConferenceProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
Country/TerritoryUnited States
CitySan Jose, CA
Period22/03/0424/03/04

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