Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

Jun Kai Zhao; Yi Wei Chiu; Shyh Jye Jou; Yuan Hua Chu

doi:10.1109/ISOCC.2014.7087594

Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

Jun Kai Zhao, Yi Wei Chiu, Shyh Jye Jou, Yuan Hua Chu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

Original language	English
Title of host publication	ISOCC 2014 - International SoC Design Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	114-115
Number of pages	2
ISBN (Electronic)	9781479951260
DOIs	https://doi.org/10.1109/ISOCC.2014.7087594
State	Published - 16 Apr 2015
Event	11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 3 Nov 2014 → 6 Nov 2014

Publication series

Name	ISOCC 2014 - International SoC Design Conference

Conference

Conference	11th International SoC Design Conference, ISOCC 2014
Country/Territory	Korea, Republic of
City	Jeju
Period	3/11/14 → 6/11/14

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10.1109/ISOCC.2014.7087594

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Zhao, J. K., Chiu, Y. W., Jou, S. J., & Chu, Y. H. (2015). Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS). In ISOCC 2014 - International SoC Design Conference (pp. 114-115). [7087594] (ISOCC 2014 - International SoC Design Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2014.7087594

@inproceedings{473c7ec24c694d338ca15d21a7e79773,

title = "Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)",

abstract = "In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.",

author = "Zhao, {Jun Kai} and Chiu, {Yi Wei} and Jou, {Shyh Jye} and Chu, {Yuan Hua}",

year = "2015",

month = apr,

day = "16",

doi = "10.1109/ISOCC.2014.7087594",

language = "English",

series = "ISOCC 2014 - International SoC Design Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "114--115",

booktitle = "ISOCC 2014 - International SoC Design Conference",

address = "United States",

note = "null ; Conference date: 03-11-2014 Through 06-11-2014",

}

Zhao, JK, Chiu, YW, Jou, SJ & Chu, YH 2015, Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS). in ISOCC 2014 - International SoC Design Conference., 7087594, ISOCC 2014 - International SoC Design Conference, Institute of Electrical and Electronics Engineers Inc., pp. 114-115, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 3/11/14. https://doi.org/10.1109/ISOCC.2014.7087594

Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS). / Zhao, Jun Kai; Chiu, Yi Wei; Jou, Shyh Jye et al.

ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 114-115 7087594 (ISOCC 2014 - International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

AU - Zhao, Jun Kai

AU - Chiu, Yi Wei

AU - Jou, Shyh Jye

AU - Chu, Yuan Hua

PY - 2015/4/16

Y1 - 2015/4/16

N2 - In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

AB - In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

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M3 - Conference contribution

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BT - ISOCC 2014 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 3 November 2014 through 6 November 2014

ER -

Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

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