@inproceedings{473c7ec24c694d338ca15d21a7e79773,
title = "Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)",
abstract = "In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.",
author = "Zhao, {Jun Kai} and Chiu, {Yi Wei} and Jou, {Shyh Jye} and Chu, {Yuan Hua}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 11th International SoC Design Conference, ISOCC 2014 ; Conference date: 03-11-2014 Through 06-11-2014",
year = "2015",
month = apr,
day = "16",
doi = "10.1109/ISOCC.2014.7087594",
language = "English",
series = "ISOCC 2014 - International SoC Design Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "114--115",
booktitle = "ISOCC 2014 - International SoC Design Conference",
address = "美國",
}