Substrate-Strained Silicon Technology: Process Integration

H. C.H. Wang; Y. P. Wang; S. J. Chen; C. H. Ge; S. M. Ting; J. Y. Kung; R. L. Hwang; H. K. Chiu; L. C. Sheu; P. Y. Tsai; L. G. Yao; S. C. Chen; H. J. Tao; Y. C. Yeo; W. C. Lee; Chen-Ming Hu

doi:10.1109/IEDM.2003.1269166

Substrate-Strained Silicon Technology: Process Integration

H. C.H. Wang^*, Y. P. Wang, S. J. Chen, C. H. Ge, S. M. Ting, J. Y. Kung, R. L. Hwang, H. K. Chiu, L. C. Sheu, P. Y. Tsai, L. G. Yao, S. C. Chen, H. J. Tao, Y. C. Yeo, W. C. Lee, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to journal › Conference article › peer-review

33 Scopus citations

Abstract

We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in I_on-I_off characteristics without correction for self-heating effect is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased off-state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

Original language	English
Pages (from-to)	61-64
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2003.1269166
State	Published - 2003
Event	IEEE International Electron Devices Meeting - Washington, DC, United States Duration: 8 Dec 2003 → 10 Dec 2003

Access to Document

10.1109/IEDM.2003.1269166

Cite this

Wang, H. C. H., Wang, Y. P., Chen, S. J., Ge, C. H., Ting, S. M., Kung, J. Y., Hwang, R. L., Chiu, H. K., Sheu, L. C., Tsai, P. Y., Yao, L. G., Chen, S. C., Tao, H. J., Yeo, Y. C., Lee, W. C., & Hu, C.-M. (2003). Substrate-Strained Silicon Technology: Process Integration. Technical Digest - International Electron Devices Meeting, 61-64. https://doi.org/10.1109/IEDM.2003.1269166

@article{0f9b3aec922441debd99d4efd7d4662f,

title = "Substrate-Strained Silicon Technology: Process Integration",

abstract = "We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in Ion-Ioff characteristics without correction for self-heating effect is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased off-state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.",

author = "Wang, {H. C.H.} and Wang, {Y. P.} and Chen, {S. J.} and Ge, {C. H.} and Ting, {S. M.} and Kung, {J. Y.} and Hwang, {R. L.} and Chiu, {H. K.} and Sheu, {L. C.} and Tsai, {P. Y.} and Yao, {L. G.} and Chen, {S. C.} and Tao, {H. J.} and Yeo, {Y. C.} and Lee, {W. C.} and Chen-Ming Hu",

year = "2003",

doi = "10.1109/IEDM.2003.1269166",

language = "English",

pages = "61--64",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting ; Conference date: 08-12-2003 Through 10-12-2003",

}

TY - JOUR

T1 - Substrate-Strained Silicon Technology

T2 - IEEE International Electron Devices Meeting

AU - Wang, H. C.H.

AU - Wang, Y. P.

AU - Chen, S. J.

AU - Ge, C. H.

AU - Ting, S. M.

AU - Kung, J. Y.

AU - Hwang, R. L.

AU - Chiu, H. K.

AU - Sheu, L. C.

AU - Tsai, P. Y.

AU - Yao, L. G.

AU - Chen, S. C.

AU - Tao, H. J.

AU - Yeo, Y. C.

AU - Lee, W. C.

AU - Hu, Chen-Ming

PY - 2003

Y1 - 2003

N2 - We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in Ion-Ioff characteristics without correction for self-heating effect is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased off-state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

AB - We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in Ion-Ioff characteristics without correction for self-heating effect is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased off-state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

UR - http://www.scopus.com/inward/record.url?scp=0842331412&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2003.1269166

DO - 10.1109/IEDM.2003.1269166

M3 - Conference article

AN - SCOPUS:0842331412

SN - 0163-1918

SP - 61

EP - 64

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

Y2 - 8 December 2003 through 10 December 2003

ER -

Substrate-Strained Silicon Technology: Process Integration

Abstract

Access to Document

Other files and links

Fingerprint

Cite this