Substrate-Strained Silicon Technology: Process Integration

H. C.H. Wang*, Y. P. Wang, S. J. Chen, C. H. Ge, S. M. Ting, J. Y. Kung, R. L. Hwang, H. K. Chiu, L. C. Sheu, P. Y. Tsai, L. G. Yao, S. C. Chen, H. J. Tao, Y. C. Yeo, W. C. Lee, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

30 Scopus citations


We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in Ion-Ioff characteristics without correction for self-heating effect is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased off-state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

Original languageEnglish
Pages (from-to)61-64
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 2003
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: 8 Dec 200310 Dec 2003


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