Subnanometer scaling of HfO2/metal electrode gate stacks

Jeff J. Peterson*, Chadwin D. Young, Joel Barnett, Sundar Gopalan, Jim Gutt, Choong Ho Lee, Hong Jyh Li, Tuo-Hung Hou, Yudong Kim, Chan Lim, Nirmal Chaudhary, Naim Moumen, Byoung Hun Lee, Gennadi Bersuker, George A. Brown, Peter M. Zeitzoff, Mark I. Gardner, Robert W. Murto, Howard R. Huff

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

34 Scopus citations


The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, (i) reduction of the bottom interfacial layer (BIL) using NH3 interface engineering, (ii) thickness reduction of the HfO2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH3 BIL with scaled HfO 2/metal gates and 0.81 nm EOT using the O3 BIL with scaled HfO2/metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.

Original languageEnglish
Pages (from-to)G164-G167
JournalElectrochemical and Solid-State Letters
Issue number8
StatePublished - 2004


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