Submicron CMOS thermal noise modeling from an RF perspective

Jeffrey J. Ou*, Xiaodong Jin, Chen-Ming Hu, Paul R. Gray

*Corresponding author for this work

    Research output: Contribution to journalConference articlepeer-review

    13 Scopus citations


    Continuous scaling of submicron CMOS technologies will soon make low cost, wireless system-on-a-chip communication products possible. The ultimate goal of these systems is to integrate the entire RF front-end with DSP together on a single chip. One key issue to the success of this CMOS RF system LSI chip implementation is how to accurately predict circuit performance using simulators such as SPICE. This will require accurate RF AC and noise models. The latter is essential for optimizing the noise performance which will in turn lead to a low power design. Recently, several CMOS RF models have been proposed for improvement on the accuracy of AC analysis at high frequencies (Ou et al, 1998). However, the accuracy of the existing noise models is not satisfactory for submicron CMOS. In this paper, a physics-based RF thermal noise model is proposed for submicron CMOS devices with a channel thermal noise model, resulting in a nearly bias-independent noise factor /spl gamma/. This model shows good agreement with measured RF noise data across a wide range of bias conditions.

    Original languageEnglish
    Pages (from-to)151-152
    Number of pages2
    JournalDigest of Technical Papers - Symposium on VLSI Technology
    StatePublished - 1 Dec 1999
    EventProceedings of the 1999 Symposium on VLSI Technology - Kyoto, Jpn
    Duration: 14 Jun 199916 Jun 1999


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