Sub-word and reduced-width booth multipliers for DSP applications

Meng Hung Tsai; Yi Ting Chen; Wen Sheng Cheng; Jun Xian Teng; Shyh-Jye Jou

doi:10.1109/ISCAS.2002.1010289

Sub-word and reduced-width booth multipliers for DSP applications

Meng Hung Tsai^*, Yi Ting Chen, Wen Sheng Cheng, Jun Xian Teng, Shyh-Jye Jou

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, based on the low-power version of parallel Booth multiplier we will show one novel sub-word parallel (SWP) multiplier and one low-error reduced-width multiplier. In the new SWP multiplier, it can finish one n by n multiplication or two n/2 by n/2 multiplications or the multiplication of two n/2 complex numbers in the same architecture. In the low-error reduced-width multiplier, an input number dependent compensation vector is derived that is superior to other proposed results in error performance and operation speed. The implementation results of 16 by 16 to 16 case show that the area is 50.67% and the critical path delay is 66.18% of the original Booth multiplier.

Original language	English
Pages (from-to)	III/575-III/578
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.2002.1010289
State	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: 26 May 2002 → 29 May 2002

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title = "Sub-word and reduced-width booth multipliers for DSP applications",

abstract = "In this paper, based on the low-power version of parallel Booth multiplier we will show one novel sub-word parallel (SWP) multiplier and one low-error reduced-width multiplier. In the new SWP multiplier, it can finish one n by n multiplication or two n/2 by n/2 multiplications or the multiplication of two n/2 complex numbers in the same architecture. In the low-error reduced-width multiplier, an input number dependent compensation vector is derived that is superior to other proposed results in error performance and operation speed. The implementation results of 16 by 16 to 16 case show that the area is 50.67% and the critical path delay is 66.18% of the original Booth multiplier.",

author = "Tsai, {Meng Hung} and Chen, {Yi Ting} and Cheng, {Wen Sheng} and Teng, {Jun Xian} and Shyh-Jye Jou",

year = "2002",

doi = "10.1109/ISCAS.2002.1010289",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

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T1 - Sub-word and reduced-width booth multipliers for DSP applications

AU - Tsai, Meng Hung

AU - Chen, Yi Ting

AU - Cheng, Wen Sheng

AU - Teng, Jun Xian

AU - Jou, Shyh-Jye

PY - 2002

Y1 - 2002

N2 - In this paper, based on the low-power version of parallel Booth multiplier we will show one novel sub-word parallel (SWP) multiplier and one low-error reduced-width multiplier. In the new SWP multiplier, it can finish one n by n multiplication or two n/2 by n/2 multiplications or the multiplication of two n/2 complex numbers in the same architecture. In the low-error reduced-width multiplier, an input number dependent compensation vector is derived that is superior to other proposed results in error performance and operation speed. The implementation results of 16 by 16 to 16 case show that the area is 50.67% and the critical path delay is 66.18% of the original Booth multiplier.

AB - In this paper, based on the low-power version of parallel Booth multiplier we will show one novel sub-word parallel (SWP) multiplier and one low-error reduced-width multiplier. In the new SWP multiplier, it can finish one n by n multiplication or two n/2 by n/2 multiplications or the multiplication of two n/2 complex numbers in the same architecture. In the low-error reduced-width multiplier, an input number dependent compensation vector is derived that is superior to other proposed results in error performance and operation speed. The implementation results of 16 by 16 to 16 case show that the area is 50.67% and the critical path delay is 66.18% of the original Booth multiplier.

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M3 - Conference article

AN - SCOPUS:0036290696

SN - 0271-4310

VL - 3

SP - III/575-III/578

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

Sub-word and reduced-width booth multipliers for DSP applications

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