Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

C. Y. He; K. H. Tang; T. S. Chen; K. Y. Chang; C. H. Lin; K. Sato; Shyh-Jye Jou; P. H. Chen; Hung-Ming Chen; B. D. Rong; K. Itoh

doi:10.1109/A-SSCC47793.2019.9056897

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, Hung-Ming Chen, B. D. Rong, K. Itoh

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	227-230
Number of pages	4
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056897
State	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Keywords

5T bit (memory) cell
gate-boosting driver
low-power array
Sub-0.5 V SRAM

Access to Document

10.1109/A-SSCC47793.2019.9056897

Cite this

He, C. Y., Tang, K. H., Chen, T. S., Chang, K. Y., Lin, C. H., Sato, K., Jou, S.-J., Chen, P. H., Chen, H.-M., Rong, B. D., & Itoh, K. (2019). Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 227-230). Article 9056897 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056897

@inproceedings{f20da81bf35b42c1b0f13d58dbc34bd8,

title = "Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line",

abstract = "A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.",

keywords = "5T bit (memory) cell, gate-boosting driver, low-power array, Sub-0.5 V SRAM",

author = "He, {C. Y.} and Tang, {K. H.} and Chen, {T. S.} and Chang, {K. Y.} and Lin, {C. H.} and K. Sato and Shyh-Jye Jou and Chen, {P. H.} and Hung-Ming Chen and Rong, {B. D.} and K. Itoh",

year = "2019",

month = nov,

doi = "10.1109/A-SSCC47793.2019.9056897",

language = "English",

series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "227--230",

booktitle = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",

address = "United States",

note = "15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

}

He, CY, Tang, KH, Chen, TS, Chang, KY, Lin, CH, Sato, K, Jou, S-J, Chen, PH, Chen, H-M, Rong, BD & Itoh, K 2019, Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056897, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 227-230, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056897

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line. / He, C. Y.; Tang, K. H.; Chen, T. S. et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 227-230 9056897 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

AU - He, C. Y.

AU - Tang, K. H.

AU - Chen, T. S.

AU - Chang, K. Y.

AU - Lin, C. H.

AU - Sato, K.

AU - Jou, Shyh-Jye

AU - Chen, P. H.

AU - Chen, Hung-Ming

AU - Rong, B. D.

AU - Itoh, K.

PY - 2019/11

Y1 - 2019/11

N2 - A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.

AB - A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.

KW - 5T bit (memory) cell

KW - gate-boosting driver

KW - low-power array

KW - Sub-0.5 V SRAM

UR - http://www.scopus.com/inward/record.url?scp=85083668063&partnerID=8YFLogxK

U2 - 10.1109/A-SSCC47793.2019.9056897

DO - 10.1109/A-SSCC47793.2019.9056897

M3 - Conference contribution

AN - SCOPUS:85083668063

T3 - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

SP - 227

EP - 230

BT - Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Y2 - 4 November 2019 through 6 November 2019

ER -

He CY, Tang KH, Chen TS, Chang KY, Lin CH, Sato K et al. Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 227-230. 9056897. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056897

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this