Sub-nanometer high-k gate stack scaling using the HF-last/NH3 anneal interface

Jeff J. Peterson; Joel Barnett; Chadwin D. Young; Tuo-Hung Hou; Jim Gutt; Sundar Gopalan; Choong Ho Lee; Hong Jyb Li; Naim Moumen; Nirmal Chaudhary; Byoung Hun Lee; Gennadi Bersuker; Peter M. Zeitzoff; George A. Brown; Pat Lysaght; Mark Gardner; Robert W. Murto; Howard R. Huff

Sub-nanometer high-k gate stack scaling using the HF-last/NH₃ anneal interface

Jeff J. Peterson^*, Joel Barnett, Chadwin D. Young, Tuo-Hung Hou, Jim Gutt, Sundar Gopalan, Choong Ho Lee, Hong Jyb Li, Naim Moumen, Nirmal Chaudhary, Byoung Hun Lee, Gennadi Bersuker, Peter M. Zeitzoff, George A. Brown, Pat Lysaght, Mark Gardner, Robert W. Murto, Howard R. Huff

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

The scaling of high-k gate stacks using an HF-last/NH₃ anneal bottom interface was evaluated for EOT, N_it, and mobility effects on HfC₂polysilicon and HfO₂/metal gate transistors. TEM analysis of HF-last/NH₃ bottom interface layers was also done, showing HF-Iast/NH₃ and O₃ bottom interface layer thickness to be identical within the resolution of the measurement. Electrical characterization showed that use of HF-last/NH₃ anneal bottom interface reduces the EOT of high-k/polysilicon gate devices by 0.3 nm and high-k/metal gate devices by about 0.15-0.2 nm with respect to the corresponding ozonated (O₃) interface sample. Charge pumping on the HF-last/NH₃ anneal bottom interface indicated N_it density of ∼5×10¹⁰ cm^-2, slightly greater than the O₃ interface control, with mobilities nearly equivalent to those in corresponding O₃ interface devices. These data show NH₃ bottom interface chemistry to be highly effective in scaling the EOT of HfO ₂/polysilicon and HfO₂/metal gate stacks while giving nearly equivalent electrical characteristics in transistors fabricated using this method.

Original language	English
Pages	93-99
Number of pages	7
State	Published - Oct 2003
Event	Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium - Orlando, FL., United States Duration: 12 Oct 2003 → 17 Oct 2003

Conference

Conference	Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium
Country/Territory	United States
City	Orlando, FL.
Period	12/10/03 → 17/10/03

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Peterson, J. J., Barnett, J., Young, C. D., Hou, T.-H., Gutt, J., Gopalan, S., Lee, C. H., Li, H. J., Moumen, N., Chaudhary, N., Lee, B. H., Bersuker, G., Zeitzoff, P. M., Brown, G. A., Lysaght, P., Gardner, M., Murto, R. W., & Huff, H. R. (2003). Sub-nanometer high-k gate stack scaling using the HF-last/NH₃ anneal interface. 93-99. Paper presented at Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium, Orlando, FL., United States.

@conference{3b0bab7641424fdda17a50b77a471e82,

title = "Sub-nanometer high-k gate stack scaling using the HF-last/NH3 anneal interface",

abstract = "The scaling of high-k gate stacks using an HF-last/NH3 anneal bottom interface was evaluated for EOT, Nit, and mobility effects on HfC2polysilicon and HfO2/metal gate transistors. TEM analysis of HF-last/NH3 bottom interface layers was also done, showing HF-Iast/NH3 and O3 bottom interface layer thickness to be identical within the resolution of the measurement. Electrical characterization showed that use of HF-last/NH3 anneal bottom interface reduces the EOT of high-k/polysilicon gate devices by 0.3 nm and high-k/metal gate devices by about 0.15-0.2 nm with respect to the corresponding ozonated (O3) interface sample. Charge pumping on the HF-last/NH3 anneal bottom interface indicated Nit density of ∼5×1010 cm-2, slightly greater than the O3 interface control, with mobilities nearly equivalent to those in corresponding O3 interface devices. These data show NH3 bottom interface chemistry to be highly effective in scaling the EOT of HfO 2/polysilicon and HfO2/metal gate stacks while giving nearly equivalent electrical characteristics in transistors fabricated using this method.",

author = "Peterson, {Jeff J.} and Joel Barnett and Young, {Chadwin D.} and Tuo-Hung Hou and Jim Gutt and Sundar Gopalan and Lee, {Choong Ho} and Li, {Hong Jyb} and Naim Moumen and Nirmal Chaudhary and Lee, {Byoung Hun} and Gennadi Bersuker and Zeitzoff, {Peter M.} and Brown, {George A.} and Pat Lysaght and Mark Gardner and Murto, {Robert W.} and Huff, {Howard R.}",

year = "2003",

month = oct,

language = "English",

pages = "93--99",

note = "Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium ; Conference date: 12-10-2003 Through 17-10-2003",

}

Peterson, JJ, Barnett, J, Young, CD, Hou, T-H, Gutt, J, Gopalan, S, Lee, CH, Li, HJ, Moumen, N, Chaudhary, N, Lee, BH, Bersuker, G, Zeitzoff, PM, Brown, GA, Lysaght, P, Gardner, M, Murto, RW & Huff, HR 2003, 'Sub-nanometer high-k gate stack scaling using the HF-last/NH₃ anneal interface', Paper presented at Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium, Orlando, FL., United States, 12/10/03 - 17/10/03 pp. 93-99.

Sub-nanometer high-k gate stack scaling using the HF-last/NH₃ anneal interface. / Peterson, Jeff J.; Barnett, Joel; Young, Chadwin D. et al.
2003. 93-99 Paper presented at Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium, Orlando, FL., United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Sub-nanometer high-k gate stack scaling using the HF-last/NH3 anneal interface

AU - Peterson, Jeff J.

AU - Barnett, Joel

AU - Young, Chadwin D.

AU - Hou, Tuo-Hung

AU - Gutt, Jim

AU - Gopalan, Sundar

AU - Lee, Choong Ho

AU - Li, Hong Jyb

AU - Moumen, Naim

AU - Chaudhary, Nirmal

AU - Lee, Byoung Hun

AU - Bersuker, Gennadi

AU - Zeitzoff, Peter M.

AU - Brown, George A.

AU - Lysaght, Pat

AU - Gardner, Mark

AU - Murto, Robert W.

AU - Huff, Howard R.

PY - 2003/10

Y1 - 2003/10

N2 - The scaling of high-k gate stacks using an HF-last/NH3 anneal bottom interface was evaluated for EOT, Nit, and mobility effects on HfC2polysilicon and HfO2/metal gate transistors. TEM analysis of HF-last/NH3 bottom interface layers was also done, showing HF-Iast/NH3 and O3 bottom interface layer thickness to be identical within the resolution of the measurement. Electrical characterization showed that use of HF-last/NH3 anneal bottom interface reduces the EOT of high-k/polysilicon gate devices by 0.3 nm and high-k/metal gate devices by about 0.15-0.2 nm with respect to the corresponding ozonated (O3) interface sample. Charge pumping on the HF-last/NH3 anneal bottom interface indicated Nit density of ∼5×1010 cm-2, slightly greater than the O3 interface control, with mobilities nearly equivalent to those in corresponding O3 interface devices. These data show NH3 bottom interface chemistry to be highly effective in scaling the EOT of HfO 2/polysilicon and HfO2/metal gate stacks while giving nearly equivalent electrical characteristics in transistors fabricated using this method.

AB - The scaling of high-k gate stacks using an HF-last/NH3 anneal bottom interface was evaluated for EOT, Nit, and mobility effects on HfC2polysilicon and HfO2/metal gate transistors. TEM analysis of HF-last/NH3 bottom interface layers was also done, showing HF-Iast/NH3 and O3 bottom interface layer thickness to be identical within the resolution of the measurement. Electrical characterization showed that use of HF-last/NH3 anneal bottom interface reduces the EOT of high-k/polysilicon gate devices by 0.3 nm and high-k/metal gate devices by about 0.15-0.2 nm with respect to the corresponding ozonated (O3) interface sample. Charge pumping on the HF-last/NH3 anneal bottom interface indicated Nit density of ∼5×1010 cm-2, slightly greater than the O3 interface control, with mobilities nearly equivalent to those in corresponding O3 interface devices. These data show NH3 bottom interface chemistry to be highly effective in scaling the EOT of HfO 2/polysilicon and HfO2/metal gate stacks while giving nearly equivalent electrical characteristics in transistors fabricated using this method.

UR - http://www.scopus.com/inward/record.url?scp=3042717138&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:3042717138

SP - 93

EP - 99

T2 - Cleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium

Y2 - 12 October 2003 through 17 October 2003

ER -

Sub-nanometer high-k gate stack scaling using the HF-last/NH₃ anneal interface

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