Sub μW noise reduction for CIC hearing aids

Cheng Wen Wei*, Sheng Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    2 Scopus citations


    This paper presents a sub μW noise reduction design to enhance speech for completely-in-the-canal (CIC) type hearing aids by optimizing its algorithm and associated architecture. In algorithm optimization, a low-complexity mixed perceptual-discrete wavelet packet transform (P-DWPT) and fast Hartley transform (FHT) are adopted for spectral decomposition and reconstruction. A simple yet efficient denoise method with 4-zone-voice activity detection (VAD) supports a consonant protection to improve speech quality and a skip scheme to reduce power consumption. In the designed architecture, mixed P-DWPT and FHT are folded into one 8-by-8 configurable butterfly computation unit with on-time scheduling for low power operation. The circuit is implemented with 0.18-μm CMOS process and consumes only 0.65 μW power at 1.0 V with a speech quality that is comparable to that achieved using other high-complexity algorithms.

    Original languageEnglish
    Article number5740627
    Pages (from-to)937-947
    Number of pages11
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number5
    StatePublished - May 2012


    • Acoustic noise
    • VLSI
    • hearing aids
    • low power design
    • speech processing


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