Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-μm BCD Process

Chao Yang Chen, Jian Hsing Lee, Karuna Nidhi, Tzer Yaa Bin, Geeng Lih Lin, Ming-Dou Ker*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

An abnormal lower latchup immunity is really induced by the guard rings which were originally applied to prevent latchup occurrence between the HV-PMOS and LV-PMOS in a 0.15-μm BCD process. The parasitic npn BJT, that exits between the guard rings from HV-NW (biased at highvoltage VDDH) to the LV-NW (biased at low-voltage VDDL), may cause a holding voltage lower than the voltage difference between VDDH and VDDL. To apply the guard rings for latchup prevention, the study results reported in this work are very important to the foundries and the IC design houses.

Original languageEnglish
Title of host publication2021 IEEE International Reliability Physics Symposium, IRPS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728168937
DOIs
StatePublished - Mar 2021
Event2021 IEEE International Reliability Physics Symposium, IRPS 2021 - Virtual, Monterey, United States
Duration: 21 Mar 202124 Mar 2021

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2021-March
ISSN (Print)1541-7026

Conference

Conference2021 IEEE International Reliability Physics Symposium, IRPS 2021
Country/TerritoryUnited States
CityVirtual, Monterey
Period21/03/2124/03/21

Keywords

  • Guard Rings
  • High-Voltage CMOS
  • Latchup
  • Latchup Prevention
  • bipolar-CMOS-DMOS (BCD) process

Fingerprint

Dive into the research topics of 'Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-μm BCD Process'. Together they form a unique fingerprint.

Cite this