Study on random telegraph noise of high-κ/metal-gate gate-all-around poly-Si nanowire transistors

You Tai Chang; Yueh Lin Tsai; Kang Ping Peng; Chun Jung Su; Pei Wen Li; Horng Chih Lin

doi:10.7567/1347-4065/ab5b67

Study on random telegraph noise of high-κ/metal-gate gate-all-around poly-Si nanowire transistors

You Tai Chang, Yueh Lin Tsai, Kang Ping Peng, Chun Jung Su, Pei Wen Li, Horng Chih Lin^*

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-κ oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals. We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side.

Original language	English
Article number	SGGA04
Number of pages	5
Journal	Japanese journal of applied physics
Volume	59
Issue number	SG
DOIs	https://doi.org/10.7567/1347-4065/ab5b67
State	Published - 1 Apr 2020

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title = "Study on random telegraph noise of high-κ/metal-gate gate-all-around poly-Si nanowire transistors",

abstract = "In this paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-κ oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals. We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side.",

author = "Chang, {You Tai} and Tsai, {Yueh Lin} and Peng, {Kang Ping} and Su, {Chun Jung} and Li, {Pei Wen} and Lin, {Horng Chih}",

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AU - Chang, You Tai

AU - Tsai, Yueh Lin

AU - Peng, Kang Ping

AU - Su, Chun Jung

AU - Li, Pei Wen

AU - Lin, Horng Chih

PY - 2020/4/1

Y1 - 2020/4/1

N2 - In this paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-κ oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals. We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side.

AB - In this paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-κ oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals. We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side.

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Study on random telegraph noise of high-κ/metal-gate gate-all-around poly-Si nanowire transistors

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