Study on ESD protection design with stacked low-voltage devices for high-voltage applications

Chia Tsen Dai, Ming-Dou Ker

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    10 Scopus citations

    Abstract

    ESD protection with stacked low-voltage (LV) devices are proposed to form an area-efficient design for high-voltage (HV) applications in a 0.25-μm HV BCD process. By using the stacked configuration, the LV devices can provide scalable triggering voltage (Vt1) and holding voltage (Vh) for various HV applications. Experimental results in silicon chip have verified that the stacked LV devices can exhibit a higher ESD robustness per unit layout area as comparing to the ESD clamp circuit with HV device.

    Original languageEnglish
    Title of host publication2014 IEEE International Reliability Physics Symposium, IRPS 2014
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Print)9781479933167
    DOIs
    StatePublished - 1 Jan 2014
    Event52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States
    Duration: 1 Jun 20145 Jun 2014

    Publication series

    NameIEEE International Reliability Physics Symposium Proceedings
    ISSN (Print)1541-7026

    Conference

    Conference52nd IEEE International Reliability Physics Symposium, IRPS 2014
    Country/TerritoryUnited States
    CityWaikoloa, HI
    Period1/06/145/06/14

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