Structural approach for performance driven ECC circuit synthesis

Chau-Chin Su; Kathy Y. Chen; Shyh-Jye Jou

doi:10.1109/ASPDAC.1997.600065

Structural approach for performance driven ECC circuit synthesis

Chau-Chin Su^*, Kathy Y. Chen, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.

Original language	English
Pages	89-94
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.1997.600065
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn Duration: 28 Jan 1997 → 31 Jan 1997

Conference

Conference	Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
City	Chiba, Jpn
Period	28/01/97 → 31/01/97

Access to Document

10.1109/ASPDAC.1997.600065

Cite this

@conference{5f93fb899cb44b1e9d21b700a5b42f9e,

title = "Structural approach for performance driven ECC circuit synthesis",

abstract = "ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.",

author = "Chau-Chin Su and Chen, {Kathy Y.} and Shyh-Jye Jou",

year = "1997",

month = jan,

day = "1",

doi = "10.1109/ASPDAC.1997.600065",

language = "English",

pages = "89--94",

note = "Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC ; Conference date: 28-01-1997 Through 31-01-1997",

}

TY - CONF

T1 - Structural approach for performance driven ECC circuit synthesis

AU - Su, Chau-Chin

AU - Chen, Kathy Y.

AU - Jou, Shyh-Jye

PY - 1997/1/1

Y1 - 1997/1/1

N2 - ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.

AB - ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.

UR - http://www.scopus.com/inward/record.url?scp=0030672484&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.1997.600065

DO - 10.1109/ASPDAC.1997.600065

M3 - Paper

AN - SCOPUS:0030672484

SP - 89

EP - 94

T2 - Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC

Y2 - 28 January 1997 through 31 January 1997

ER -

Structural approach for performance driven ECC circuit synthesis

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this