Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien Hao Chen; T. L. Lee; Tuo-Hung Hou; C. L. Chen; C. C. Chen; J. W. Hsu; K. L. Cheng; Y. H. Chiu; H. J. Tao; Y. Jin; C. H. Diaz; S. C. Chen; M. S. Liang

doi:10.1109/VLSIT.2004.1345390

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien Hao Chen^*, T. L. Lee, Tuo-Hung Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, M. S. Liang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

136 Scopus citations

Abstract

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

Original language	English
Title of host publication	2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
Publisher	IEEE
Pages	56-57
Number of pages	2
ISBN (Print)	0-7803-8289-7
DOIs	https://doi.org/10.1109/VLSIT.2004.1345390
State	Published - 1 Oct 2004
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: 15 Jun 2004 → 17 Jun 2004

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISSN (Print)	0743-1562

Conference

Conference	2004 Symposium on VLSI Technology - Digest of Technical Papers
Country/Territory	United States
City	Honolulu, HI
Period	15/06/04 → 17/06/04

Keywords

Nitride
SMT
Stained-Si
Stress

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10.1109/VLSIT.2004.1345390

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Chen, C. H., Lee, T. L., Hou, T.-H., Chen, C. L., Chen, C. C., Hsu, J. W., Cheng, K. L., Chiu, Y. H., Tao, H. J., Jin, Y., Diaz, C. H., Chen, S. C., & Liang, M. S. (2004). Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application. In 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS (pp. 56-57). (Digest of Technical Papers - Symposium on VLSI Technology). IEEE. https://doi.org/10.1109/VLSIT.2004.1345390

@inproceedings{7384bd4f5b4b4574ac95d79926d297d8,

title = "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application",

abstract = "An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.",

keywords = "Nitride, SMT, Stained-Si, Stress",

author = "Chen, {Chien Hao} and Lee, {T. L.} and Tuo-Hung Hou and Chen, {C. L.} and Chen, {C. C.} and Hsu, {J. W.} and Cheng, {K. L.} and Chiu, {Y. H.} and Tao, {H. J.} and Y. Jin and Diaz, {C. H.} and Chen, {S. C.} and Liang, {M. S.}",

year = "2004",

month = oct,

day = "1",

doi = "10.1109/VLSIT.2004.1345390",

language = "English",

isbn = "0-7803-8289-7",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "IEEE",

pages = "56--57",

booktitle = "2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

}

Chen, CH, Lee, TL, Hou, T-H, Chen, CL, Chen, CC, Hsu, JW, Cheng, KL, Chiu, YH, Tao, HJ, Jin, Y, Diaz, CH, Chen, SC & Liang, MS 2004, Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application. in 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS. Digest of Technical Papers - Symposium on VLSI Technology, IEEE, pp. 56-57, 2004 Symposium on VLSI Technology - Digest of Technical Papers, Honolulu, HI, United States, 15/06/04. https://doi.org/10.1109/VLSIT.2004.1345390

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application. / Chen, Chien Hao; Lee, T. L.; Hou, Tuo-Hung et al.
2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS. IEEE, 2004. p. 56-57 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

AU - Chen, Chien Hao

AU - Lee, T. L.

AU - Hou, Tuo-Hung

AU - Chen, C. L.

AU - Chen, C. C.

AU - Hsu, J. W.

AU - Cheng, K. L.

AU - Chiu, Y. H.

AU - Tao, H. J.

AU - Jin, Y.

AU - Diaz, C. H.

AU - Chen, S. C.

AU - Liang, M. S.

PY - 2004/10/1

Y1 - 2004/10/1

N2 - An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

AB - An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

KW - Nitride

KW - SMT

KW - Stained-Si

KW - Stress

UR - http://www.scopus.com/inward/record.url?scp=4544382132&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2004.1345390

DO - 10.1109/VLSIT.2004.1345390

M3 - Conference contribution

AN - SCOPUS:4544382132

SN - 0-7803-8289-7

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 56

EP - 57

BT - 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS

PB - IEEE

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

Chen CH, Lee TL, Hou TH, Chen CL, Chen CC, Hsu JW et al. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application. In 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS. IEEE. 2004. p. 56-57. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2004.1345390

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

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