@inproceedings{c5355e0fe6444f7595c3cca9592e2417,
title = "Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity",
abstract = "Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-μm BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.",
author = "Tang, {Kai Neng} and Liao, {Seian Feng} and Ming-Dou Ker and Chiou, {Hwa Chyi} and Huang, {Yeh Jen} and Tsai, {Chun Chien} and Jou, {Yeh Ning} and Lin, {Geeng Lih}",
year = "2015",
month = aug,
day = "3",
doi = "10.1109/APEMC.2015.7175270",
language = "English",
series = "2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "325--328",
booktitle = "2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015",
address = "United States",
note = "null ; Conference date: 25-05-2015 Through 29-05-2015",
}