Stability and performance optimization of heterochannel monolithic 3-D SRAM cells considering interlayer coupling

This paper extensively evaluates the stability and performance of heterochannel 6T/8T SRAM cells integrated in monolithic 3-D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. This paper indicates that stacking the NFET tier over the PFET tier results in larger design margins for cell robustness and performance. Furthermore, the partition of 3-D layout design among distinct layers shows profound impacts on the stability, standby leakage, and performance of monolithic 3-D SRAM cells. Compared with the Si-based cells, the use of heterochannel devices increases the improvements of monolithic 3-D design over the 2-D counterparts and emerges as a suitable candidate for future monolithic 3-D IC applications.